The present invention relates to a digital exchange apparatus and more particularly, to an automatic phase control circuit in a broad range exchange apparatus for handling high speed data.
Recently, demand has arisen for a broad range exchange for processing high speed signals which include a moving image as their main component. Such a broad range exchange apparatus deals with high speed signals of several hundreds of Mb/s such as moving images, which a conventional voice range exchange apparatus does not. Thus, it is necessary for highways in respective directions to be synchronized with each other.
FIGS. 1A and 1B are structural views of the prior art system.
Signals are inputted from highways H1 and H2 and flip flop F/F provided within interface circuits I1 and I2 receives data at a clock CK generated from master clock circuit 10. Then, flip-flop F/F provides the output to time divisional switching unit 11. A detailed circuit is not disclosed for time divisional switching unit 11. However, the exchange of data from respective interface circuits I1 and I2 is conducted by time divisional switching unit 11.
Master clock circuit 10 controls a time divisional switch provided in time divisional switching unit 11 through delay circuit 12.
In such a system, as shown in FIG. 1A, in order to obtain a matching of signals operated in time divisional switching unit 11, the length of clock lines from master clock circuit 10 to interface circuits I1 and I2 and further the length of the data lines from flip-flops F/F within interface circuits I1 and I2 to time divisional switching unit 11 should be made the same. This is because, if the lengths of these lines are different, the timings in the time divisional switching unit 11 are different, thereby causing an error.
As shown in FIG. 1B, delay circuits T1 and T2 are provided between interface circuits I1 and I2 and time divisional switching unit 11. Data in a highway from interface circuits I1 and I2 are delayed by a predetermined time and the delay time of delay circuits T1 and T2, respectively, are different in respective channels.
In such a broad band exchange, a delay adjustment is performed by equalizing the length of the data lines and clock lines or by inserting delay circuits. The system obtained by combining apparatuses previously recited in FIGS. 1A and 1B are also reviewed.
In the above system, a delay adjustment should be conducted for respective highways H1 and H2. Thus, when the system is enlarged, such a system is not realistic.
In contrast, there is a system for providing exchange body 13 with a simple elastic function.
FIG. 2 is a structural view of the prior art system. As shown in FIG. 2, respective highways H3 and H4, and frames F3 and F4, are obtained by interface circuits I3 and I4 and added to phase adjustment circuit 15 of exchange body 13. Flip-flops F/F of interface circuits I3 and I4 receive data in synchronization with a clock from master clock circuit 14. The clocks outputted from master clock circuit 14 are added in phase adjustment circuit 15 through respective interface circuits I3 and I4 and the data in respective highways H3 and H4 are matched with those based on these clocks and on frames F3 and F4, and are thereby inputted to time divisional switching unit 11.
Phase adjustment circuit 15 and time divisional switching unit 11 perform an exchange by using a clock transmitted from master clock circuit 14 through delay circuit 16. The clock in master clock circuit 14 is different from the clock applied to flip-flops F/F in interface circuits and the synchronized clock and frame pulses are transmitted via respective highways and are synchronized with the master clock and master frame pulse in phase adjustment circuit 15, thereby to perform a clock transfer operation. Thus, synchronization is achieved by a simple elastic function.
FIG. 3 is a detailed structural view of "a prior art phase adjustment circuit"; Respective highways (input HW#1-#n) provide the data, which is inputted together with a clock and a frame pulse (input CK#1-#n/input FP#1-#n) synchronized with respective highways. Input HW#1 is inputted to shift register SFR11 of k bits and k is sufficiently small for the number m of bits of a frame. Further, m is an integer multiplication of k. A shift clock of shift register SFR11 is input CK#1. Control unit C1 forms a latch pulse having a period of k bits from input CK#1 and input FP#1 and is inputted to flip-flop F/F1 as a clock. The speed of the signal is then 1/k in flip-flop F/F1. A similar process is applied to other highways and these shift registers operate in synchronization with a clock in respective highways.
A latch pulse (*) formed by master control unit 17 from a master clock and a master frame is inputted to shift register SFR12 with a load. The output of flip-flop F/F1 is simultaneously latched and thereafter shifted by a master clock (**). All the data of the highway is outputted as output HW#1 in a synchronized state. With the above structure, a phase difference of up to k bits can be absorbed.
FIG. 4 is a timing chart of the prior art phase adjustment circuit shown in FIG. 3. It shows a timing chart where k is 4 bits and n is 4. When respective inputs HW#1 to #4 are inputted at different timings, respective inputs HW#1 to #4 are applied to corresponding shift registers SFR1n and are shifted in accordance with respective individual clocks. On the other hand, respective control units C1-Cn produce respective latch pulses .circle. 4' .circle. 8' .circle. 12' .circle. 16' . These pulses are latched by flip-flops F/Fn and subjected to a speed conversion (serial to parallel conversion). At this time, master clock .circle. 17' and master frame .circle. 18' are inputted so that a latch pulse can be formed when respective frame pulses end and output HW#n is provided at a timing shown in .circle. 20' . Therefore, according to the above construction, phase shifting of up to k bits can be absorbed and it is not necessary to perform an equalization of a highway as shown in FIG. 1A, and the system structure's freedom is increased.
However, even where the above elastic function is provided, respective clocks should be determined in accordance with a phase of master clock .circle. 17' and master frame .circle. 18' . Therefore, there is a problem that it is necessary to perform a careful phase adjustment.
Further, when the system is expanded, the phase adjustment can be conducted by considering respective phases. Thus, if the system becomes large, such phase adjustment also becomes difficult to conduct.